APPLICATION A6 / ACCELERATED COMPUTING
GPU direct I/O and compression.
Accelerators changed where scientific data has to be. CLIO Core now reaches into the GPU: kernels submit I/O to IOWarp without leaving the device, GPU-resident data spills to host memory and NVMe, and data can be compressed on the GPU before it moves. The research builds on NVIDIA technologies such as CUDA, cuFile, NIXL, and nvCOMP.
Can scientific data move to and from GPU memory as a first-class tier, without a detour through the CPU?
AI-infused workflows compute on GPUs but still read and write through the host: the kernel ends, the CPU copies, the file system writes, and the GPU waits. Every bounce costs bandwidth and time.
Model memory has the same shape. The KV cache of LLM inference grows with context length and overflows GPU memory, turning inference into a storage-hierarchy problem.
The workflow, stage by stage.
- Issue I/O from the GPU
GPU-side primitives let CUDA, ROCm, and SYCL kernels submit work to CLIO without exiting the kernel.
CLIO Core GPU runtime - Offload payloads
GPU-resident vectors are backed by transfer-engine storage, with a GPU and host-memory page cache that spills to NVMe and brings data back on demand.
GPU vector · block devices - Compress on the device
nvCOMP, cuSZ, cuSZp, ndzip, and ZFP for SYCL shrink data before it moves; a dynamic system chooses the method for the workflow.
CLIO compression - Remove the CPU hop
Current source builds provide NVIDIA cuFile and NIXL paths. Earlier research explored a BaM-style GPU page cache and a Linux kernel module that gave GPUs their own NVMe queues; those prototypes remain in archived source.
GPU I/O · archived prototypes
What the work has produced.
Primitives let GPU kernels submit I/O commands to CLIO without exiting the kernel, and a dynamic compression system chooses a method for the workflow.[1]
CONDITIONS · Source builds onlyCLIO Core includes GPU-resident vectors, GPU compression backends, a cuFile adapter, and NIXL transport support in its source builds.[1]
CONDITIONS · Optional source builds; GPU validation depends on the backend and some tests remain opt-inCharacterization of GPUDirect data transfer through NVIDIA NIXL for AI workloads.[2]
Related team research with Argonne collaborators treats the LLM KV cache as a tier: PKAS schedules inference with the cache in view, and PagedEviction prunes cache blocks for long contexts.[3][4]
The instruments involved.
GPU runtime, GPU vectors, GPU compression, and cuFile and NIXL adapters, in CUDA, ROCm, and SYCL source builds.
Open source ↗02 / ComponentThe CLIO stackHow the accelerator and operating-system layers fit under the runtime.
Read more →03 / ComponentPublicationsNIXL characterization and KV-cache research.
Read more →Next steps.
- Publish GPU offload measurements with GPU model, interconnect, storage, and workload stated.
- Bring GPU tests into continuous integration on GPU runners.
- Record the 2026 demonstration of GPU payload offload with CLIO Core CUDA kernels.
Who should get in touch
GPU systems researchers, inference-serving teams, and facilities with GPU-attached NVMe or GPUDirect-capable storage.
Sources
- CLIO Core GPU, compression, and cuFile adapter sources
- Muradli, Ye, Logan, Kougkas, Sun. Insights into GPUDirect data transfer through NIXL benchmarking. IEEE eScience 2025 (poster and extended abstract)
- Ye, Maurya, Chitty-Venkata, Nicolae, Kougkas, Sun. PKAS: Predictive KVCache-aware scheduling for faster LLM and transformer inferences. HPDC 2026
- Chitty-Venkata, Ye, Raskar, Kougkas, Sun, Emani, Vishwanath, Nicolae. PagedEviction: Structured block-wise KV cache pruning for efficient LLM inference. Findings of EACL 2026